1. Field of the Invention
The present invention relates to a method of manufacturing an image display apparatus.
2. Related Background Art
A display having an electron source substrate in which a plurality of field emission electron-emitting devices (hereinafter referred to as FEDs) or a plurality of surface conduction electron-emitters (hereinafter referred to as SCEs) are arranged in matrix corresponding to phosphors for respective pixels is provided as a planer self-light-emission type image display apparatus.
As disclosed in Japanese Patent Application Laid-Open No. H07-235255, the SCE can be subjected to an “activation process” to improve electron emission characteristics. The “activation process” is performed by repeatedly applying a pulse voltage to an electron-emitting region in an atmosphere in which an activation material containing, for example, carbon or a carbon compound is supplied to the electron-emitting region.
As disclosed in Japanese Patent Application Laid-Open No. 2000-243223, the FED and the SCE can be subjected to a “preparative driving process” to improve the stability of electron emission characteristics. The “preparative driving process” is a driving method of driving the electron-emitting device at a voltage V1 determined from a predetermined relational expression and then performing normal driving at a voltage V2 of a voltage range determined from a predetermined relational expression.
A manufacturing method and a manufacturing apparatus for performing the “activation process” on an electron source substrate in which the SCEs are arranged in matrix are disclosed in, for example, Japanese Patent No. 3087847.
In Japanese Patent No. 3087847, an energization operation of the “activation process” is performed on an electron source in which the plurality of electron-emitting devices are connected to one another through a common wiring by simultaneously applying a voltage to each of the plurality of electron-emitting devices through the common wiring. Japanese Patent No. 3087847 shows that a voltage effectively applied to each of the electron-emitting devices is deviated from a desirable value by voltage drop caused by wiring resistance. As disclosed in Japanese Patent No. 3087847, a current If flowing through each of the electron-emitting devices or a current flowing through the wiring connected to the respective electron-emitting devices is measured and the voltage drop caused by wiring resistance is compensated based on the measured current value to apply a voltage to each of the electron-emitting devices or the wiring connected to the respective electron-emitting devices.
A manufacturing method and a manufacturing apparatus for performing the “preparative driving process” on an electron source substrate in which the electron-emitting devices are arranged in matrix are disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-243292. In Japanese Patent Application Laid-Open No. 2000-243292, an energization operation of the “preparative driving process” is performed on an electron source in which the plurality of electron-emitting devices are connected to one another through a common wiring by simultaneously applying a voltage to each of the plurality of electron-emitting devices through the common wiring.
When the electron source including the plurality of electron-emitting devices is applied to an image display apparatus such as a flat panel display, the uniformity among electron emission characteristics of the respective electron-emitting devices is required in order to ensure the uniformity of a display image. Therefore, a method of realizing a desirable electron emission characteristic with high repeatability is demanded to manufacture the electron-emitting device. In addition, a method of minimizing an electron emission characteristic difference among the electron-emitting devices is demanded to manufacture the electron source including the plurality of electron-emitting devices arranged on the same substrate.
In addition to the electron-emitting device such as the surface conduction electron-emitter, for example, an EL device can be provided as an image display device. An arrangement in which a light emitting layer of an electroluminescent display is formed by the application of a voltage is disclosed in U.S. Pat. No. 4,826,727.
In order to improve the display performance of the image display apparatus, it is necessary to improve the uniformity among characteristics of the image display devices. More specifically, in the case of the image display apparatus using the electron-emitting devices as the image display devices, it is necessary to realize the uniformity among the electron emission characteristics of the respective electron-emitting devices of the electron source. When the uniformity among the electron emission characteristics is to be realized, it is useful that voltage values effectively applied to the electron-emitting region are more uniformed in the activation process and the preparative driving process.
When the activation process and the preparative driving process are to be performed on an electron source in which a large number of electron-emitting devices are connected in matrix or an image display apparatus including the electron source, it is necessary to simultaneously select a plurality of electron-emitting devices to apply a voltage to each of the devices at the request of shortening a process time. When the voltage is simultaneously applied to each of the plurality of electron-emitting devices, the voltage drop caused by wiring resistance becomes significant, so that a difference among wiring potentials (node potentials) in node positions in which the respective electron-emitting devices are arranged cannot be neglected. A shape of a distribution of the node potentials is not limited to a constant shape and thus is changed according to current values flowing thorough the respective electron-emitting devices. Therefore, in order to apply a uniform voltage to each of the electron-emitting devices, it is necessary to predict a voltage drop quantity with high precision to add a compensation voltage to a terminal voltage. In order to shorten the process time, it is necessary to complete calculation for predicting the voltage drop quantity at short times.
The above-mentioned requirements are made for the formation of the EL device which is caused by the application of a voltage.